• DocumentCode
    1518589
  • Title

    Testing embedded-core-based system chips

  • Author

    Zorian, Yervant ; Marinissen, Erik Jan ; Dey, Sujit

  • Author_Institution
    LogicVision Inc., San Jose, CA, USA
  • Volume
    32
  • Issue
    6
  • fYear
    1999
  • fDate
    6/1/1999 12:00:00 AM
  • Firstpage
    52
  • Lastpage
    60
  • Abstract
    Recently, designers have been embedding reusable modules to build on-chip systems that form rich libraries of predesigned, preverified building blocks. These embedded cores make it easier to import technology to a new system and differentiate the corresponding product by leveraging intellectual property advantages. Most importantly, design reuse shortens the time-to-market for new systems. The attributes that make system chips built with embedded IP cores an attractive methodology-design reuse, heterogeneity, reconfigurability, and customizability-also make testing and debugging these chips a complex challenge. The authors review the various alternatives for testing embedded cores and describe solutions and proposed standards that are expected to play a key role in developing the core based design paradigm
  • Keywords
    embedded systems; industrial property; integrated circuit testing; microprocessor chips; reconfigurable architectures; core based design paradigm; customizability; design reuse; embedded IP cores; embedded-core-based system chip testing; intellectual property advantages; on-chip systems; preverified building blocks; proposed standards; reconfigurability; reusable modules; rich libraries; system chips; Automatic testing; CMOS logic circuits; CMOS technology; Circuit testing; Hardware; Logic testing; Manufacturing processes; Random access memory; System testing; System-on-a-chip;
  • fLanguage
    English
  • Journal_Title
    Computer
  • Publisher
    ieee
  • ISSN
    0018-9162
  • Type

    jour

  • DOI
    10.1109/2.769444
  • Filename
    769444