DocumentCode :
1518630
Title :
An MWPC readout chip for high rate environment
Author :
Kano, H. ; Fukunaga, C. ; Ikeno, M. ; Sasaki, O. ; Sato, K. ; Matsuura, S.
Author_Institution :
Dept. of Phys., Tokyo Metropolitan Univ., Japan
Volume :
48
Issue :
3
fYear :
2001
fDate :
6/1/2001 12:00:00 AM
Firstpage :
509
Lastpage :
513
Abstract :
An application-specified integration circuit (ASIC) has been fabricated in order to readout data from a multiwire proportional chamber (MWPC) that is installed in a high-rate environment, 16 channels and an ancillary control circuit are packed in a chip, and a channel consists of an LVDS receiver and 100-stage shift register array for delay. Hit data from the chamber is once inputted in the shift register array, and is outputted when the trigger signal is set. If a channel contains a signal during a gate followed by the trigger, the channel is regarded as containing a hit. The primary purpose for constructing the chip is for test beam and cosmic ray test of ATLAS thin gap chambers (TGC), which are used for the muon-trigger signal generation. The architecture of the ASIC is simple and independent from the specific readout scheme of ATLAS TGC. It will be found that the ASTC is adopted easily for any readout scheme of an MWPC like detector
Keywords :
application specific integrated circuits; multiwire proportional chambers; nuclear electronics; readout electronics; ASIC; MWPC; multiwire proportional chamber; readout chip; thin gap chambers; Application specific integrated circuits; Circuit testing; Delay; Physics; Pipelines; Shift registers; Signal processing; Switches; Synchronization; Variable speed drives;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/23.940108
Filename :
940108
Link To Document :
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