Title :
A New 2T Contact Coupling Gate MTP Memory in Fully CMOS Compatible Process
Author :
Lien, Chiu-Wang ; Wu, Haw-Yun ; Tsai, Cheng-Wei ; Huang, Chen-Mei ; Chih, Yue-Der ; Lee, Te-Liang ; Lin, Chrong Jung
Author_Institution :
Inst. of Electron. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fDate :
7/1/2012 12:00:00 AM
Abstract :
A new fully logic process compatible 2T multitime programmable (MTP) memory cell has been introduced for embedded logic nonvolatile memory (NVM) applications. The cell adopts a novel contact coupling gate structure as an additional control gate for highly efficient operation and high-density memory applications. A new 2T n-channel MTP 2-Kb memory test chip has been also successfully demonstrated on pure 0.18- CMOS logic process without extra masking or process step. Furthermore, the embedded 2T MTP cell performs an efficiently program/erase operation by CHE injection and FN tunnel with highly reliable endurance and retention characteristics.
Keywords :
CMOS logic circuits; logic gates; random-access storage; 2T contact coupling gate multitime programmable memory cell; CHE injection; CMOS compatible process; CMOS logic process; FN tunnel; contact coupling gate structure; control gate; embedded logic nonvolatile memory; fully logic process; memory size 2 KByte; program-erase operation; retention characteristics; size 0.18 mum; CMOS integrated circuits; Couplings; Logic gates; Nonvolatile memory; Stress; Threshold voltage; Transistors; Contact coupling; NVM; embedded; logic compatible memory; logic nonvolatile memory (NVM); multitime programmable (MTP);
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2012.2196518
