Title :
Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set
Author :
Chang, Chip-Hong ; Low, Jeremy Yung Shern
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
Abstract :
Scaling in RNS has always been conceived as a performance bottleneck similar to the residue-to-binary conversion problem due to the inefficient intermodulo operation. In this paper, a simple and fast scaling algorithm for the three-moduli set {2n - 1, 2n, 2n + 1} RNS is proposed. The complexity of intermodulo operation has been resolved by a new formulation of scaling an integer in RNS domain by one of its moduli. By elegant exploitation of the Chinese Remainder Theorem and the number theoretic properties for this moduli set, the design can be readily implemented by a standard cell based design methodology. The low cost VLSI architecture without any read-only memory (ROM) makes it easier to fuse into and pipeline with other residue arithmetic operations of a RNS-based processor to increase the throughput rate. The proposed RNS scaler possesses zero scaling error and has a critical path delay of only 2[log2n]+ 9 units in unit-gate model. Besides the scaled residue numbers, the scaled integer in normal binary representation is also produced as a byproduct of this process, which saves the residue-to-binary converter when the binary representation of scaled integer is also required. Our experimental results show that the proposed RNS scaler is smaller and faster than the most area-efficient adder-based design and the fastest ROM-based design besides being the most power efficient among all scalers evaluated for the same three-moduli set.
Keywords :
VLSI; logic design; residue number systems; Chinese remainder theorem; RNS domain; RNS scaler; RNS-based processor; VLSI architecture; critical path delay; fast scaling algorithm; inefficient intermodulo operation; normal binary representation; number theoretic properties; residue arithmetic operations; residue-to-binary conversion problem; residue-to-binary converter; scaled integer; scaled residue numbers; three-moduli set; unit-gate model; zero scaling error; Algorithm design and analysis; Complexity theory; Computer architecture; Delay; Digital signal processing; Hardware; Throughput; Chinese remainder theorem; full-adder-based architecture; inner product step processor; residue number system; scaling;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2011.2142950