Title :
Hybrid carry-select statistical carry look-ahead adder
Author :
Corsonello, P. ; Perri, S. ; Cocorullo, G.
Author_Institution :
Dept. of Electron. Eng. & Appl. Math., Calabria Univ., Italy
fDate :
4/1/1999 12:00:00 AM
Abstract :
A new high-performance variable time adder is presented which is based on the statistical carry look-ahead addition technique. The new circuit uses carry-select stages to reduce the critical path. A 56 bit adder designed for and realised using 0.5 μm CMOS technology shows an average addition time of ~1.28 ns
Keywords :
CMOS logic circuits; adders; carry logic; 0.5 micron; 1.28 ns; CMOS technology; carry look-ahead adder; hybrid carry-select statistical CLA adder; variable time adder;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19990375
