Title :
Low complexity bit-parallel multipliers for GF(2m) with generator polynomial xm+xk+1
Author :
Elia, M. ; Leone, M. ; Visentin, C.
Author_Institution :
Dipt. di Elettronica, Politecnico di Torino, Italy
fDate :
4/1/1999 12:00:00 AM
Abstract :
A low complexity bit-parallel standard basis multiplier for GF(2 m) with polynomial generator xm+xk+1 is presented. The proposed multiplier uses a significantly smaller number of XOR/AND gates than the fastest known multipliers, while having a comparable logarithmic computing time
Keywords :
computational complexity; digital arithmetic; logic circuits; logic gates; multiplying circuits; polynomials; AND gates; XOR gates; bit-parallel multipliers; logarithmic computing time; low complexity multipliers; polynomial generator; standard basis multiplier;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19990407
