• DocumentCode
    1518760
  • Title

    Low complexity bit-parallel multipliers for GF(2m) with generator polynomial xm+xk+1

  • Author

    Elia, M. ; Leone, M. ; Visentin, C.

  • Author_Institution
    Dipt. di Elettronica, Politecnico di Torino, Italy
  • Volume
    35
  • Issue
    7
  • fYear
    1999
  • fDate
    4/1/1999 12:00:00 AM
  • Firstpage
    551
  • Lastpage
    552
  • Abstract
    A low complexity bit-parallel standard basis multiplier for GF(2 m) with polynomial generator xm+xk+1 is presented. The proposed multiplier uses a significantly smaller number of XOR/AND gates than the fastest known multipliers, while having a comparable logarithmic computing time
  • Keywords
    computational complexity; digital arithmetic; logic circuits; logic gates; multiplying circuits; polynomials; AND gates; XOR gates; bit-parallel multipliers; logarithmic computing time; low complexity multipliers; polynomial generator; standard basis multiplier;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19990407
  • Filename
    769476
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1518760