DocumentCode
1519475
Title
A Parallel Efficient Architecture for Large Cryptographically Robust n × k (k>n/2) Mappings
Author
Mukhopadhyay, Debdeep ; Chowdhury, Dibakar Roy
Author_Institution
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Volume
60
Issue
3
fYear
2011
fDate
3/1/2011 12:00:00 AM
Firstpage
375
Lastpage
385
Abstract
We present a scalable, modular, memoryless, and reconfigurable parallel architecture to generate cryptographically robust mappings, which are useful in the construction of stream and block ciphers. It has been theoretically proved that the proposed architecture can be reconfigured to generate a large number of mappings, all of which have high nonlinearity, satisfies Strict Avalanche Criterion (SAC) and is robust against linear and differential cryptanalysis. The architecture can be also used to optimize the resiliency and algebraic degree. The architecture has been found to scale easily to handle large number of input variables, which is an important criterion in realizing nonlinear combiners for stream ciphers using Boolean functions.
Keywords
Boolean functions; cryptography; parallel architectures; reconfigurable architectures; Boolean functions; block cipher construction; cryptographically robust mappings; differential cryptanalysis; linear cryptanalysis; reconfigurable parallel architecture; stream cipher construction; strict avalanche criterion; Boolean functions; S-Box; cryptographic robustness; scalable architecture.; stream cipher;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.2010.136
Filename
5487499
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