A 5.5 GHz low-power PLL using 0.18-µm CMOS technology

Author

Jeng-Han Tsai ; Shao-Wei Huang ; Jian-Ping Chou

Author_Institution

Dept. of Appl. Electron. Technol., Nat. Taiwan Normal Univ., Taipei, Taiwan

fYear

2014

fDate

19-23 Jan. 2014

Firstpage

205

Lastpage

207

Abstract

This paper presents a fully-integrated 5.5 GHz low-power consumption phase-locked loop (PLL) on standard 0.18-μm CMOS process. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) divider, the 5.5 GHz PLL achieves low power consumption of 9.23 mW. In addition, a rail-to-rail buffer amplifier is incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. The measured phase noises are -85 dBc/Hz and -116.6 dBc/Hz at 1 MHz and 10 MHz frequency offsets, respectively.

Keywords

CMOS analogue integrated circuits; clocks; field effect MMIC; low-power electronics; microwave amplifiers; phase locked loops; phase noise; transformers; voltage-controlled oscillators; CMOS technology; TSPC divider; frequency 5.5 GHz; fully-integrated low-power consumption; high speed phase clock divider; low-power PLL; phase locked loop; phase noise; power 9.23 mW; rail-to-rail buffer amplifier; size 0.18 mum; transformer feedback VCO; true single phase clock divider; CMOS integrated circuits; CMOS technology; Frequency measurement; Phase frequency detector; Phase locked loops; Semiconductor device measurement; Voltage-controlled oscillators; CMOS; Phase-locked loop (PLL); lower power; radio frequency integration circuit (RFIC);

fLanguage

English

Publisher

ieee

Conference_Titel

Radio and Wireless Symposium (RWS), 2014 IEEE

Conference_Location

Newport Beach, CA

Print_ISBN

978-1-4799-2298-7

Type

conf

DOI

10.1109/RWS.2014.6830071

Filename

6830071