DocumentCode
1519675
Title
A systolic architecture for fast stack sequential decoders
Author
Lavoie, Pierre ; Haccoun, David ; Savaria, Yvon
Author_Institution
Dept. of Nat. Defence, Defence Res. Establ., Ottawa, Ont., Canada
Volume
42
Issue
234
fYear
1994
Firstpage
324
Lastpage
335
Abstract
The troublesome operation of reordering the stack in stack sequential decoders is alleviated by storing the nodes in a systolic priority queue that delivers the true top node in a short and constant amount of time. A new systolic priority queue is described that allows each decoding step, including retrieval, reordering and storage of the nodes, to take place in a single clock period. A complete decoder architecture designed around this queue is compared to a conventional stack-bucket architecture from both speed and cost points of view. The proposed decoder architecture appears to be faster, affordable, and compatible with convolutional codes having long memory and high coding rate
Keywords
VLSI; convolutional codes; decoding; queueing theory; systolic arrays; VLSI; convolutional codes; decoder architecture; fast stack sequential decoders; node storage; parallel entry systolic priority queue; reordering; retrieval; systolic architecture; Clocks; Computer architecture; Computer errors; Convolutional codes; Costs; Decoding; Error correction; Extremities; Forward error correction; Very large scale integration;
fLanguage
English
Journal_Title
Communications, IEEE Transactions on
Publisher
ieee
ISSN
0090-6778
Type
jour
DOI
10.1109/TCOMM.1994.577044
Filename
577044
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