DocumentCode
1520304
Title
ASMD with duty cycle correction scheme for high-speed DRAM
Author
Jang, Seong-Jin ; Jun, Young-Hyun ; Lee, Jae-Goo ; Bai-Sun Kon
Author_Institution
Sch. of Electr. & Comput. Eng, SungKyunKwan Univ., Suwon, South Korea
Volume
37
Issue
16
fYear
2001
fDate
8/2/2001 12:00:00 AM
Firstpage
1004
Lastpage
1006
Abstract
An analogue synchronous mirror delay with duty cycle-correction scheme (ASMDCC), to improve the data transmission performance between DRAM and system, is proposed. The ASMDCC achieves duty cycle correction and clock synchronisation at once within two clock cycles, by using a half value current source. The simulation results show the duty cycle of the internal clock is stabilised with less than ±100 ps deviation from 50% for the wide duty cycle range
Keywords
DRAM chips; analogue processing circuits; circuit simulation; clocks; delays; high-speed integrated circuits; synchronisation; ASMD; analogue synchronous mirror delay; clock synchronisation; dual edge triggering systems; duty cycle-correction scheme; half value current source; high-speed DRAM; internal clock duty cycle stabilisation; simulation results; wide duty cycle range;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20010717
Filename
941796
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