Title :
On the Electron and Hole Tunneling in a
Gate Stack With Extreme Interfacial-Layer Scaling
Author :
Ando, Takashi ; Sathaye, Ninad D. ; Murali, Kota V R M ; Cartier, Eduard A.
Author_Institution :
T.J. Watson Res. Center, IBM, Yorktown Heights, NY, USA
fDate :
7/1/2011 12:00:00 AM
Abstract :
With decreasing SiO2 interfacial-layer (IL) thickness, gate currents in SiO2/HfO2 dual-layer gate stacks are observed to undergo drastic changes. For an IL thickness below 3 Å, a transition from hole-current-dominated transport to electron-current-dominated transport is observed near operating bias conditions in p-channel field-effect transistors. A tunneling simulation based on the transfer-matrix approach suggests that the band offsets for the SiO2 and HfO2 layers are reduced in the submonolayer IL regime ( <; 3 Å), promoting the transition in the conduction mechanism.
Keywords :
field effect transistors; hafnium compounds; matrix algebra; monolayers; silicon compounds; tunnelling; HfO2; SiO2; conduction mechanism; dual-layer gate stacks; electron tunneling; electron-current-dominated transport; extreme interfacial-layer scaling; gate currents; gate stack tunneling; hole tunneling; hole-current-dominated transport; p-channel field-effect transistors; submonolayer IL regime; transfer-matrix approach; Charge carrier processes; Current measurement; Dielectrics; Logic gates; Silicon; Substrates; Tunneling; Direct tunneling; hafnium oxide; scavenging; transfer matrix;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2011.2146751