Viability Study of All-III–V SRAM for Beyond-22-nm Logic Circuits

Author

Oh, Saeroonter ; Wong, H. S Philip

Author_Institution

Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA

Volume

32

Issue

7

fYear

2011

fDate

7/1/2011 12:00:00 AM

Firstpage

877

Lastpage

879

Abstract

A physics-based compact model for III-V FETs is developed for logic circuit applications. The model is applied to study sub-22-nm technology 6T-SRAM cells with InGaAs MOSFETs. The pull-down and pass gate combination is optimized for maximum cell stability. The drawbacks of having a weak III-V PMOS as the pull-up device in a SRAM cell are investigated. In this letter, we propose a minimum requirement for PMOS strength for all-III-V SRAM to be viable in a logic chip. Also, by assuming a high-performance PMOS, we observe a 26% higher static current noise margin and a two times faster write speed compared to conventional SRAM.

Keywords

III-V semiconductors; MOSFET circuits; SRAM chips; integrated circuit modelling; logic circuits; 6T-SRAM cells; III-V FET; InGaAs; MOSFET; PMOS strength; all-III-V SRAM; logic chip; logic circuit applications; maximum cell stability; pass gate combination; physics-based compact model; pull-down combination; pull-up device; size 22 nm; static current noise margin; viability study; weak III-V PMOS; write speed; FETs; Indium gallium arsenide; Integrated circuit modeling; Logic gates; Random access memory; Silicon; Stability analysis; Alternative channel FET; III–V; SPICE simulation; SRAM; compact model; logic circuits;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2011.2148092

Filename

5771044