A 200-MHz CMOS I/Q downconverter

Author

Yim, Darwin T S ; Ling, Curtis C.

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong

Volume

46

Issue

6

fYear

1999

fDate

6/1/1999 12:00:00 AM

Firstpage

808

Lastpage

810

Abstract

This CMOS in-phase/quadrature (I/Q) downconverter circuit is based on a modified sampling architecture which permits very precise I/Q phase and amplitude balance across the entire 200-MHz bandwidth of operation. At a radio frequency of 201 MHz, the downconverter uses a local oscillator sampling rate of 40 MHz and an intermediate frequency of 1 MHz. The circuit is implemented in a 0.5-μm process and has a measured I/Q balance of better than 0.33 dB and 0.7°, with a power consumption of 20 mW from a 3-V supply, and a die area of 0.9 mm²

Keywords

CMOS analogue integrated circuits; frequency convertors; radio receivers; signal sampling; 0.5 micron; 1 MHz; 20 mW; 200 MHz; 3 V; 40 MHz; CMOS I/Q downconverter; amplitude balance; die area; in-phase/quadrature circuit; intermediate frequency; local oscillator; power consumption; sampling architecture; Bandwidth; Circuit topology; Clocks; Differential amplifiers; Operational amplifiers; Pulse generation; Radio frequency; Sampling methods; Signal generators; Signal sampling;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.769788

Filename

769788