Title :
Sigma-delta ADC with reduced sample rate multibit quantizer
Author :
Qin, Wei ; Hu, Bo ; Ling, Xieting
Author_Institution :
Syst. State Key Lab., Fudan Univ., Shanghai, China
fDate :
6/1/1999 12:00:00 AM
Abstract :
Based on the well-known Leslie-Singh architecture, a new cascaded sigma-delta analog-to-digital conversion (ADC) architecture is proposed. It incorporates a multibit quantizer whose sample rate can be significantly lower than the full oversampling speed of the sigma-delta modulator. Simulation results and comparison with other architectures are given. The architecture can be a good choice to extend the use of sigma-delta ADC to high bandwidth applications
Keywords :
cascade networks; quantisation (signal); sigma-delta modulation; Leslie-Singh architecture; analog-to-digital conversion; cascaded ADC architecture; high bandwidth applications; reduced sample rate multibit quantizer; sigma-delta ADC; Analog-digital conversion; Bandwidth; CMOS process; Delta-sigma modulation; Digital-analog conversion; Filters; Multi-stage noise shaping; Noise shaping; Quantization; Transfer functions;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
