The impact of induced gate noise when simultaneously power and conjugate noise-matching MOS transistors

Author

Manku, Tajinder

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

Volume

46

Issue

6

fYear

1999

fDate

6/1/1999 12:00:00 AM

Firstpage

842

Lastpage

844

Abstract

A method for simultaneously power matching and conjugate noise matching a MOS transistor for radio frequency applications is presented in this paper. Experimental results from a 0.6 μm nMOS transistor show that the magnitude of input reactance equals the optimum noise reactance (i.e., X_in=X_opt). Using this result, the author provides a method that can be used to match the optimum noise resistance to the source resistance. The described method uses the number of gate fingers as a parameter to conjugately match for noise

Keywords

CMOS integrated circuits; MOSFET; UHF field effect transistors; UHF integrated circuits; equivalent circuits; impedance matching; integrated circuit noise; semiconductor device models; semiconductor device noise; 0.6 micron; CMOSFET; NMOSFET; RF MOS transistor; RFIC; conjugate noise matching; induced gate noise; input reactance; n-channel FET; optimum noise reactance; optimum noise resistance; power matching; radiofrequency applications; simultaneously power/noise matching; source resistance; Arithmetic; CMOS technology; Circuit noise; Digital filters; Digital signal processing chips; MOSFETs; Noise figure; Radio frequency; Signal processing algorithms; Working environment noise;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.769796

Filename

769796