Ultra-wideband, high-efficiency, on-chip mmW phased arrays with wafer-level vertical integration

Summary form only given. The explosive growth in wireless communications and the proliferation of devices with internet connectivity are swiftly leading to a detrimental congestion of the traditional radio frequency (RF) bands. For the first time, the number of “things” connected to the internet is surpassing the number of “people” and this trend is poised to continue as more devices in our homes and businesses get “smarter” and connected. To ensure the continued reliability of the “internet-of-things”, the millimeter Wave (mmW) band is being coveted as the next generation of wireless protocols. The mmW band offers large, sustained bandwidths for the end-user over shortrange (local-area) wireless links and networks. Thanks to the much smaller wavelengths in this band, antennas can be directly integrated with transceiver electronics. Moreover, on-chip packaging of antenna fronts-ends offer significant cost advantages. Nevertheless, energy dissipation in the lossy substrates have so far resulted in extremely-poor (<;10%) radiation efficiencies. Although low-loss substrates are available for mmW band, these cannot be readily integrated with CMOS processes. In this paper, we propose a new low-profile tightly-coupled antenna array topology that can be vertically integrated onto CMOS chips using a low-loss polymer (SU-8) as the antenna substrate. To do so, we first adopt the novel ultra-wideband (UWB) RF phased array designs that have only recently been demonstrated (J. P. Doane, K. Sertel and J. L. Volakis, IEEE TAP, Vol.61, 2013). The array design is further modified to conform to the wafer-level lithographic fabrication process. A key aspect of the proposed mmW array is the isolation of the radiating element from the CMOS substrate via a ground plane, resulting in unprecedented on-chip radiation efficiencies (on the order of 7080%). A fabrication process is developed using ultra-thick SU-8 dielectric - ilms, metallic feed, load, and antenna layers. A 3x3 phased array antennas consisting of 9 metal and dielectric layers are patterned on CMOS-grade substrate for testing purposes. The details of the array design, fabrication development and measurement results will be presented.