DocumentCode :
1521071
Title :
A Compact Space and Efficient Drain Current Design for Multipillar Vertical MOSFETs
Author :
Sakui, Koji ; Endoh, Tetsuo
Author_Institution :
Center for Interdiscipl. Res., Tohoku Univ., Sendai, Japan
Volume :
57
Issue :
8
fYear :
2010
Firstpage :
1768
Lastpage :
1773
Abstract :
In the vertical MOSFET, due to its device structure, the bottom of its silicon pillar has a certain resistance because there is a diffused silicon wiring area in the bottom. Thereby, this resistance becomes large in the case of the multipillar transistors and also shows asymmetric characteristics between the top and bottom nodes of the pillar. This paper is devoted to examining this resistance for the multipillar vertical MOSFETs and proposing a compact design, which can suppress the resistance influences, attain a large drain current, and achieve a higher circuit performance.
Keywords :
MOSFET; bottom node resistance; compact space and efficient drain current design; multipillar transistors; multipillar vertical MOSFET; Circuit optimization; Circuit synthesis; Contact resistance; Current density; Immune system; MOSFETs; Manufacturing; Materials science and technology; Silicon; Wiring; Bottom node resistance; multipillar MOSFETs; vertical MOSFET;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2010.2050546
Filename :
5491144
Link To Document :
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