Title :
High speed SAR ADC using fast conversion loop
Author :
Ensafdaran, Masoud ; Namgoong, Won
Author_Institution :
Univ. of Texas at Dallas, Richardson, TX, USA
Abstract :
A 10b 250MS/s SAR ADC using a fast loop is presented. The SAR loop delay is minimized using a two-speed variable clock generator, a semi-dynamic comparator and a latch based SAR logic. A metastability detection circuit with minimized self-metastability window is also proposed. The SAR ADC is implemented in 65nm CMOS process and achieves 250 MS/s with ENOB of 8.63b while dissipating 6mA at 1.2V supply.
Keywords :
CMOS logic circuits; analogue-digital conversion; asynchronous circuits; comparators (circuits); detector circuits; flip-flops; CMOS process; ENOB; SAR loop delay; bit rate 10 bit/s; current 6 mA; fast conversion loop; high speed SAR ADC; latch based SAR logic; metastability detection circuit; self-metastability window; semidynamic comparator; size 65 nm; successive approximation ADC; two-speed variable clock generator; voltage 1.2 V; CMOS integrated circuits; Clocks; Delays; Detectors; Generators; Latches; Power demand; Metastability detector; SAR; Successive Approximation ADC;
Conference_Titel :
Radio and Wireless Symposium (RWS), 2014 IEEE
Conference_Location :
Newport Beach, CA
Print_ISBN :
978-1-4799-2298-7
DOI :
10.1109/RWS.2014.6830154
