• DocumentCode
    1521134
  • Title

    Scalable 10 Gbit/s 4×20.25 μm CMOS/SIMOX ATM switch LSI circuit based on distributed contention control

  • Author

    Oki, E. ; Yamanaka, N. ; Okazaki, K. ; Ohtomo, Y.

  • Author_Institution
    NTT Network Service Syst. Labs., Tokyo, Japan
  • Volume
    35
  • Issue
    9
  • fYear
    1999
  • fDate
    4/29/1999 12:00:00 AM
  • Firstpage
    715
  • Lastpage
    716
  • Abstract
    A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput, 0.2 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption
  • Keywords
    asynchronous transfer mode; 0.25 micron; 1.25 Gbit/s; 10 Gbit/s; 7 W; ATM switch LSI circuit; CMOS/SIMOX LSI circuit; Si; distributed contention control; scalable LSI circuit;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19990428
  • Filename
    769845
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1521134