A High-Resolution ( ${< 10}~{\rm ps}$ RMS) 48-Channel Time-to-Digital Converter (TDC) Implemented in a Field Programmable Gate Array (FPGA)

A high-resolution 48-Channel Time-to-Digital Converter (TDC) implemented in a general purpose Field Programmable Gate Array (FPGA) is presented. Dedicated carry chains of the FPGA are utilized for time interpolation purposes inside a clock cycle. A counter running at the system clock frequency provides a global time stamp. These two values, along with the channel number, are stored for readout. An extra effort was made to improve the resolution beyond the intrinsic cell delay of the carry chain as well as to achieve the same resolution on all 48 channels. Due to large bin width variations a bin-by-bin calibration scheme was used. Time interval (TI) measurements between two channels were made to determine the RMS and the time resolution of a single channel. At least 6 ps single channel resolution was achieved for all channels. Additional measurements were performed to characterize the influence of the temperature and voltage variations on the RMS value and the mean as well as the sensitivity of the TDC to crosstalk. The results of these measurements are also presented in this paper.