Multiplier-free Raised-Cosine filter for binary streams using DDS

Raised-Cosine filters with over-sampled input/output are used to limit spectral bandwidth of the communication signals. Over-sampling inherently increases the number of required components in FIR filters. We aimed to reduce the number of scarse and frequently needed resources, multipliers (or selectors) and adders, and replace them with the counters and storage elements that are abundant in FPGA´s. Since the number of possible waveforms generated by FIR-filtering upsampled binary streams are finite and determined by the number of storage elements in the filter, placing these waveforms in LUTs and outputting the waveforms that correspond the inputs, greatly simplifies the FIR-filter implementation. The possibility of run-time update of LUTs makes run-time replacement of the waveforms possible. High operation frequency of the block rams allowed problem-free operation of the example filters in this work.