• DocumentCode
    1521604
  • Title

    A pipelined architecture for the multidimensional DFT

  • Author

    Yu, Sungwook ; Swartzlander, Earl E., Jr.

  • Author_Institution
    Intel Corp., Austin, TX, USA
  • Volume
    49
  • Issue
    9
  • fYear
    2001
  • fDate
    9/1/2001 12:00:00 AM
  • Firstpage
    2096
  • Lastpage
    2102
  • Abstract
    This paper presents an efficient pipelined architecture for the N m-point m-dimensional discrete Fourier transform (DFT). By using a two-level index mapping scheme that is different from the conventional decimation-in-time (DIT) or decimation-infrequency (DIF) algorithms, the conventional pipelined architecture for the one-dimensional (1-D) fast Fourier transform (FFT) can be efficiently used for the computation of higher dimensional DFTs. Compared with systolic architectures, the proposed scheme is area-efficient since the computational elements (CEs) use the minimum number of multipliers, and the number of CEs increases only linearly with respect to the dimension m. It can be easily extended to the Nm-point m-dimensional DFT with large m and/or N, and it is more flexible since the throughput can be easily varied to accommodate various area/throughput requirements
  • Keywords
    discrete Fourier transforms; pipeline processing; signal processing; area/throughput requirements; computational elements; decimation-in-time algorithm; decimation-infrequency algorithm; digital signal processing; discrete Fourier transform; multidimensional DFT; multipliers; pipelined architecture; systolic architectures; two-level index mapping; Computer architecture; Discrete Fourier transforms; Fast Fourier transforms; Fourier transforms; Multidimensional systems; Signal analysis; Signal processing algorithms; Space technology; Systolic arrays; Throughput;
  • fLanguage
    English
  • Journal_Title
    Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1053-587X
  • Type

    jour

  • DOI
    10.1109/78.942637
  • Filename
    942637