FPDR90—A Low Noise, Fast Pixel Readout Chip in 90 nm CMOS Technology

We report on the design of a prototype IC called FPDR90 dedicated for readout of hybrid pixel semiconductor detectors used for X-ray imaging applications. The FPDR90 has dimensions of 4 mm × 4 mm and was designed in CMOS 90 nm technology with 9 metal layers. The core of the IC is a matrix of 40 × 32 pixels with 100 μm × 100 μm pixel size. A 50 μm diameter circular passivation opening in each pixel allows connecting FPDR90 to a semiconductor detector using bump bonding technique. Each pixel contains a charge sensitive amplifier (CSA), a main amplifier stage, two discriminators and two 16-bit ripple counters. To minimize the effective threshold spread at the discriminators inputs, one 7-bit and one 6-bit trim DACs are used in each pixel for threshold low and threshold high respectively. The data are read out via a single LVDS output with 200 Mbps rate. Each pixel contains about 1800 transistors and has a nominal power consumption of 42 μW for nominal bias condition. The effective peaking time at the discriminator input is 28 ns and it is mainly determined by the time constants of the CSA. The gain is equal to 32 μV/e- or 64 μV/e- in the low and the high gain mode respectively. In the high gain mode the ENC without the detector is 91 e- rms and rises to 106 e- rms with stud bump-bonded pixel detector. The effective threshold spread at the discriminator input is only 0.76 mV (at one sigma level, with 7-bit trim DACs enabled), which corresponds to 12 e- rms at the input. The maximum count rate per pixel depends on the effective CSA feedback resistance. A dead time in the front-end can be set as low as 117 ns (paralyzable model). The FPDR90 can operate with two energy thresholds in the readout mode separate from exposure. Continuous readout is possible when only one threshold is used.