Title :
Estimation and Compensation of Process-Induced Variations in Nanoscale Tunnel Field-Effect Transistors for Improved Reliability
Author :
Saurabh, Sneh ; Kumar, M. Jagadesh
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Delhi, India
Abstract :
Tunnel field-effect transistors (TFETs) have extremely low leakage current, exhibit excellent subthreshold swing, and are less susceptible to short-channel effects. However, TFETs do face certain special challenges, particularly with respect to the process-induced variations in the following: 1) the channel length and 2) the thickness of the silicon thin film and gate oxide. This paper, for the first time, studies the impact of the aforementioned process variations on the electrical characteristics of a double-gate tunnel field-effect transistor (DGTFET). Using 2-D device simulations, we propose the strained DGTFET as a possible solution for effectively compensating the process-induced variations in the on-current, threshold voltage, and subthreshold swing and improving the reliability of the DGTFET.
Keywords :
elemental semiconductors; field effect transistors; semiconductor device reliability; silicon; 2D device simulations; FET; Si; double-gate tunnel field-effect transistor; improved reliability; leakage current; nanoscale tunnel field-effect transistors; process-induced variations; subthreshold swing; threshold voltage; CMOS process; CMOS technology; Double-gate FETs; Electric variables; Leakage current; Permission; Semiconductor thin films; Silicon; Threshold voltage; Tunneling; CMOS technology; process-induced variations; strain; tunnel field-effect transistor (TFET);
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2010.2054095
