A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture

This paper proposes a 0.5 V/100 MHz/sub-5 mW-operated 1-Mbit SRAM cell architecture which uses a boosted and offset-grounded data storage (BOGS) scheme. The key target of BOGS is to minimize the charge amount supplied from the embedded charge pump circuits, which are required to boost the effective gate to source voltage (V/sub 0/=V/sub GS/-V/sub T/) up to 0.8 V necessary to achieve 100 MHz operation even at 0.5 V single power supply. Thus, the key low-power strategy of BOGS is "putting the right (higher efficiency) boosted power-supply from charge pump circuit into the right position (less power consumed transistor) in a SRAM cell." This paper is focused on why BOGS can realize a greater savings of the charge amount supplied from the boosted power-line and can reduce the power dissipation to /spl les/1/30.4 and /spl les/1/3.9 compared to the previously reported negative source-line drive (NSD) scheme and negative word-line drive (NWD) scheme, respectively, while achieving a 0.5 V/100 MHz operation.