DocumentCode
1522816
Title
An insulator-lined silicon substrate-via technology with high aspect ratio
Author
Wu, Joyce H. ; Scholvin, Jörg ; del Alamo, Jesús A.
Author_Institution
MIT, Cambridge, MA, USA
Volume
48
Issue
9
fYear
2001
fDate
9/1/2001 12:00:00 AM
Firstpage
2181
Lastpage
2183
Abstract
We have developed a novel high-aspect ratio substrate-via technology in silicon that features a SiN insulator liner. In this technology, the via is completely filled with electroplated Cu. We have demonstrated vias with an aspect ratio of 30 and we have verified the integrity of the liner in vias with an aspect ratio of 8. The impedance of individual vias was measured in the microwave regime using a high-frequency test structure. The measured inductance of vias with aspect ratios between 3 and 30 approach the theoretically expected values
Keywords
MMIC; copper; elemental semiconductors; inductance; integrated circuit interconnections; microwave measurement; silicon; silicon compounds; Si-SiN-Cu; aspect ratio; high-frequency test structure; impedance; inductance; insulator-lined silicon substrate-via technology; microwave regime; Etching; Gallium arsenide; Impedance measurement; Insulation; Isolation technology; Microwave measurements; Radio frequency; Silicon compounds; Silicon on insulator technology; Testing;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.944215
Filename
944215
Link To Document