Title :
A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI
Author :
Siligaris, Alexandre ; Hamada, Yasuhiro ; Mounet, Christopher ; Raynaud, Christine ; Martineau, Baudouin ; Deparis, Nicolas ; Rolland, Nathalie ; Fukaishi, Muneo ; Vincent, Pierre
Author_Institution :
LETI, CEA, Grenoble, France
fDate :
7/1/2010 12:00:00 AM
Abstract :
A 60 GHz wideband power amplifier (PA) is fabricated in a standard CMOS SOI 65 nm process. The PA is based on two cascode stages. Input, output and inter-stage matching use coplanar wave guide (CPW) transmission lines that have low losses thanks to the high-resistivity SOI substrate (3 kΩ · cm). The PA measurements are carried out for supply voltages VDD going from 1.2 V to 2.6 V and achieve a saturation power of 10 dBm to 16.5 dBm respectively. The peak power-added efficiency (PAE) is higher than 20% for all applied VDD values.
Keywords :
CMOS integrated circuits; coplanar waveguides; power amplifiers; silicon-on-insulator; wideband amplifiers; CMOS; PAE; SOI; cascode stages; coplanar wave guide transmission lines; frequency 60 GHz; inter-stage matching; power-added efficiency; saturation power; size 65 nm; voltage 1.2 V to 2.6 V; wideband power amplifier; Broadband amplifiers; CMOS process; Coplanar transmission lines; Coplanar waveguides; Impedance matching; Power amplifiers; Power measurement; Power transmission lines; Propagation losses; Transmission line measurements; 60 GHz; CMOS; CPW; SOI; V-band; power amplifier;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2010.2049456
