Title :
A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS
Author :
Drago, Salvatore ; Leenaerts, DomineM W. ; Nauta, Bram ; Sebastiano, Fabio ; Makinwa, Kofi A A ; Breems, Lucien J.
Author_Institution :
NXP Semicond., Eindhoven, Netherlands
fDate :
7/1/2010 12:00:00 AM
Abstract :
The design of a duty-cycled PLL (DCPLL) capable of burst mode operation is presented. The proposed DCPLL is a moderately accurate low-power high-frequency synthesizer suitable for use in nodes for wireless sensor networks (WSN). Thanks to a dual loop configuration, the PLL´s total frequency error, once in lock, is less than 0.25% from 300 MHz to 1.2 GHz. It employs a fast start-up DCO which enables its operation at duty-cycles as low as 10%. Fabricated in a baseline 65 nm CMOS technology, the DCPLL circuit occupies 0.19 x 0.15 mm2 and draws 200 μA from a 1.3 V supply when generating bursts of 1 GHz signal with a 10% duty-cycle.
Keywords :
CMOS integrated circuits; UHF integrated circuits; frequency synthesizers; low-power electronics; phase locked loops; wireless sensor networks; CMOS technology; DCPLL circuit; current 200 muA; duty-cycled PLL; frequency 300 MHz to 1.2 GHz; frequency error; low-power high-frequency synthesizer; size 65 nm; voltage 1.3 V; wireless sensor networks; wireless sensor nodes; Batteries; CMOS technology; Energy consumption; Frequency synthesizers; Integrated circuit technology; Jitter; Oscillators; Phase locked loops; Phase noise; Wireless sensor networks; CMOS; PLL; WSN; duty-cycle; frequency stability; frequency synthesizer; fully integrated; ultra-low-power; wireless sensor networks;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2010.2049458
