Partial-Matching Technique in a Mixed-Mode BIST Environment

A mixed-mode built-in self-test (BIST) approach that deploys two new techniques is presented in this paper. Partial pattern matching allows the reduction of the number of patterns used for detecting random-pattern-resistant faults without relying on fault simulation. A multiple-control sequence is used to guide the linear feedback shift register (LFSR) to generate these patterns at application time. The advantages of this method include the reduction of the test data volume, the shortening of the test application time, and its reusability for logic cores on a system-on-chip (SOC).