FPGA-based high resolution synchronous conversion application in multiple sensor systems

In sensor-based systems, the correlation of sensor outputs in time is one of the key factors determining the success of the signal process performed on these outputs. To provide correlation in time, analog-digital convertors in a system must perform synchronous conversion. Although ΣΔ analog-digital convertors are widely used in sensor-based systems, due to their intrinsic hardware topology they can´t perform synchronous conversion in systems which convertors do not use a common clock source or discrete clock source frequencies are not to be controlled. In this work, digital and decimation filters in ΣΔ ADC topology are implemented in FPGA; monitoring the error in conversion time and adjusting the decimation rate of the filter according to the error during system operation synchronous conversion is performed. Possible conversion errors during decimation rate adjustment are eliminated by using dual filter structure, and synchronous conversion is achieved without loss in ΣΔ ADC performance.