Title :
Silicon stacked tunnel transistor for highspeed and high-density random access memory gain cells
Author :
Nakazato, K. ; Itoh, K. ; Mizuta, H. ; Ahmed, H.
Author_Institution :
Cavendish Lab., Hitachi Eur. Ltd., Cambridge, UK
fDate :
5/13/1999 12:00:00 AM
Abstract :
Novel stacked tunnel transistors have been fabricated on silicon dioxide using a standard 0.2 μm silicon process. From the measured characteristics it is shown that random access memory operations with 10 ns read/write times are possible in cells which occupy the area of just one transistor
Keywords :
DRAM chips; elemental semiconductors; leakage currents; silicon; tunnel transistors; 0.2 micron; 10 ns; Si stacked tunnel transistor; Si-SiO2; high-density RAM gain cells; high-speed RAM gain cells; random access memory gain cells; standard Si process;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19990574
