Investigating the Drain-Bias-Induced Degradation Behavior Under Light Illumination for InGaZnO Thin-Film Transistors

This letter investigates the effect of gate/drain bias stress in InGaZnO thin-film transistors under light illumination and in a darkened environment. Drain current-gate voltage (ID-VG) as well as capacitance-voltage (C-V) transfer curves are measured to analyze the degradation behavior. The device characteristic exhibits a positively parallel shift after the gate/drain bias stress in the dark. On the other hand, the identical stress performed under light illumination leads to not only a negative shift but also a distortion of the C-V curve in the off state. Such phenomenon can be attributed to hole-trapping-induced barrier lowering near the drain side after illuminated bias stress.