DocumentCode
1523828
Title
Chemical Oxide Interfacial Layer for the High-
-Last/Gate-Last Integration Scheme
Author
Chen, Ying-Tsung ; Fu, Ssu-I ; Chiang, Wen-Tai ; Lin, Chien-Ting ; Tsai, Shih-Hung ; Wang, Shao-Wei ; Chang, Shoou-Jinn
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Volume
33
Issue
7
fYear
2012
fDate
7/1/2012 12:00:00 AM
Firstpage
946
Lastpage
948
Abstract
The authors propose a high-k-last with gate-last integration scheme with a chemical oxide interfacial layer (IL). It was found that chemical oxide IL could form Hf-silicate at the high-k/IL interface so as to provide us a larger effective k value and a smaller equivalent oxide thickness (EOT). It was also found that the larger leakage current density for the samples with chemical oxide IL could be effectively suppressed by postdeposition annealing (PDA). Furthermore, it was found that PDA-induced larger EOT could be reduced by optimizing the metal gate stack.
Keywords
annealing; atomic layer deposition; current density; hafnium compounds; high-k dielectric thin films; leakage currents; silicon compounds; surface chemistry; EOT; Hf-SiO4; PDA; atomic layer deposition; chemical oxide IL; chemical oxide interfacial layer; equivalent oxide thickness; high-k-IL interface; high-k-last-gate-last integration scheme; leakage current density; metal gate stack optimization; postdeposition annealing; Chemicals; Current measurement; High K dielectric materials; Leakage current; Logic gates; Metals; Silicon; Equivalent oxide thickness (EOT); Si–O–Hf; high-$k$ ; postdeposition annealing (PDA); work function metal;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2012.2195292
Filename
6204313
Link To Document