Abstract :
In this paper, the phenomenon of channel hot carrier (CHC) induced degradation in transistors and its relation to ESD reliability is reviewed. The principles of CHC and the tradeoff with ESD during technology development from channel/drain engineering, including consideration for mixed voltage designs, are discussed. Also, latent damage due to ESD-induced effects on CHC is considered. Finally, it is shown how the generation of hot carriers can help in the optimization of the performance of advanced ESD protection concepts
Keywords :
CMOS integrated circuits; VLSI; electrostatic discharge; hot carriers; integrated circuit reliability; ESD; channel/drain engineering; hot carrier degradation; latent damage; mixed voltage designs; reliability; submicrometer CMOS technologies; technology development; CMOS technology; Degradation; Electrons; Electrostatic discharge; Hot carriers; MOSFETs; Protection; Reliability engineering; Silicon; Voltage;
