DocumentCode
1524174
Title
Hot carrier degradation and ESD in submicrometer CMOS technologies: how do they interact?
Author
Groeseneken, Guido V.
Author_Institution
IMEC, Leuven, Belgium
Volume
1
Issue
1
fYear
2001
fDate
3/1/2001 12:00:00 AM
Firstpage
23
Lastpage
32
Abstract
In this paper, the phenomenon of channel hot carrier (CHC) induced degradation in transistors and its relation to ESD reliability is reviewed. The principles of CHC and the tradeoff with ESD during technology development from channel/drain engineering, including consideration for mixed voltage designs, are discussed. Also, latent damage due to ESD-induced effects on CHC is considered. Finally, it is shown how the generation of hot carriers can help in the optimization of the performance of advanced ESD protection concepts
Keywords
CMOS integrated circuits; VLSI; electrostatic discharge; hot carriers; integrated circuit reliability; ESD; channel/drain engineering; hot carrier degradation; latent damage; mixed voltage designs; reliability; submicrometer CMOS technologies; technology development; CMOS technology; Degradation; Electrons; Electrostatic discharge; Hot carriers; MOSFETs; Protection; Reliability engineering; Silicon; Voltage;
fLanguage
English
Journal_Title
Device and Materials Reliability, IEEE Transactions on
Publisher
ieee
ISSN
1530-4388
Type
jour
DOI
10.1109/7298.946457
Filename
946457
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