DocumentCode
1524502
Title
A tabular method for guard strengthening, symmetrization, and operator reduction for Martin´s asynchronous design methodology
Author
Tabrizi, Nozar ; Liebelt, Michael J. ; Eshraghian, Kamran
Author_Institution
Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
Volume
46
Issue
9
fYear
1997
fDate
9/1/1997 12:00:00 AM
Firstpage
1050
Lastpage
1054
Abstract
We introduce a tabular method to perform the last two of the four phases of Martin´s compilation process for asynchronous circuit design. The method is then demonstrated with three examples, illustrating that our systematic method is very straight forward, flexible, and convenient to apply, and, hence, it lends itself to automatic compilation
Keywords
asynchronous circuits; logic design; sequential circuits; Martin´s asynchronous design; asynchronous circuit design; asynchronous sequential circuits; automatic compilation; delay insensitive circuits; formal program transformation; guard strengthening; guarded commands; operator reduction; self-timed logic; signal transition graphs; speed independent circuits; symmetrization; tabular method; Asynchronous circuits; Circuit synthesis; Clocks; Delay; Design methodology; Driver circuits; Logic design; Production; Sequential circuits; Signal synthesis;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.620487
Filename
620487
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