Design and modelling of a high performance differential bipolar self-timed microprocessor

Current interest in self-timed systems is motivated by the area, power and design effort required for the global clock of VLSI synchronous designs. A self-timed data-path, based on the ARM (Advanced RISC Machine) processor, using `micropipeline´ control techniques has been developed for a newly updated high-performance differential bipolar technology. This paper describes the architectural model produced to verify the correctness of the prototype design, and the use of the model in evaluating and enhancing the processor performance. Self-timed design comprises independent blocks whose operation depends solely on input data and unit availability. The modelling of the dynamic behaviour of blocks and the control structures required are presented. These illustrate how easily and well the self-timed operation is mapped onto the Verilog modelling language. Benchmark results on the processor indicate a factor-of-two performance improvement over a CMOS version. The system state at a particular instant is difficult to determine and the effects of interactions between modules are difficult to quantify. The use of the model to explore design changes, particularly to the buffering structures, is presented. This allows the design to be `tuned´ to the technology. It also enables a better understanding of total system behaviour