• DocumentCode
    1524994
  • Title

    Cached DRAM for ILP processor memory access latency reduction

  • Author

    Zhang, Zhao ; Zhu, Zhichun ; Zhang, Xiaodong

  • Author_Institution
    Coll. of William & Mary, Williamsburg, VA, USA
  • Volume
    21
  • Issue
    4
  • fYear
    2001
  • Firstpage
    22
  • Lastpage
    32
  • Abstract
    Cached DRAM adds a small cache onto a DRAM chip to reduce average DRAM access latency. The authors compare cached DRAM with other advanced DRAM techniques for reducing memory access latency in instruction-level-parallelism processors
  • Keywords
    DRAM chips; cache storage; memory architecture; parallel architectures; DRAM access latency; ILP; cached DRAM; instruction-level-parallelism processors; latency reduction; processor memory access latency; Bandwidth; Capacitors; Computer aided instruction; Concurrent computing; Delay; Impedance; Interleaved codes; Parallel processing; Random access memory; SDRAM;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/40.946676
  • Filename
    946676
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1524994