Title :
A real-time digital VCR encode/decode and MPEG-2 decode LSI implemented on a dual-issue RISC processor
Author :
Mohri, A. ; Yamada, A. ; Yoshida, T. ; Sato, H. ; Takata, H. ; Nakakimura, K. ; Hashizume, M. ; Shimotsuma, Y. ; Tsuchihashi, K.
Author_Institution :
Inf. Technol. R&D Center, Mitsubishi Electr. Corp., Kanagawa, Japan
fDate :
7/1/1999 12:00:00 AM
Abstract :
A real-time system large-scale-integrated circuit (LSI) for digital video cassette recorder (DVCR) encoding/decoding and MPEG-2 decoding is implemented on a dual-issue RISC processor (DRISC) with dedicated hardware optimized for video-block processing. The DRISC achieves 972-MOPS software performance and can execute fixed-length data processing at the block level as well as processing at the macro-block level and above for the DVCR/MPEG-2. The dedicated hardware for variable-length coding/decoding can encode and decode codes for both the DVCR and the MPEG-2 by changing translation tables. The dedicated hardware for video-block loading can process video-block data transfers with half-pel operations. The LSI size is 7.7×7.2 mm2 in a 0.25-μm CMOS process
Keywords :
CMOS digital integrated circuits; data compression; decoding; digital signal processing chips; large scale integration; multimedia systems; real-time systems; reduced instruction set computing; variable length codes; video coding; video recording; video tape recorders; 0.25 micron; CMOS process; MPEG-2 decode LSI; dedicated hardware; digital VCR encode/decode LSI; digital video cassette recorder; dual-issue RISC processor; fixed-length data processing; half-pel operations; macro-block level; real-time system; translation tables; variable-length coding; variable-length decoding; video-block processing; Circuits; Data processing; Decoding; Encoding; Hardware; Large scale integration; Real time systems; Reduced instruction set computing; Software performance; Video recording;
Journal_Title :
Solid-State Circuits, IEEE Journal of
