Testability aspects of folded source-coupled logic

Several low noise logic schemes for mixed mode integrated circuit design have been presented over the last few years. These logic approaches are used to diminish the level of switching noise generated by the digital part of the circuit, In the paper the testability of one of these approaches is analysed: folded source-coupled logic (FSCL). A basic FSCL inverter with two kind of realistic fault (bridge and open circuit, including floating gates) is simulated. The effects of the realistic faults in various observable magnitudes are presented and discussed, and some test approaches are suggested