Title :
Wired-OR property and improved structure of recovered energy logic (REL)
Author :
Kim, Chulwoo ; Kim, Soowon
Author_Institution :
Dept. of Electron. Eng., Korea Univ., Seoul, South Korea
fDate :
12/1/1997 12:00:00 AM
Abstract :
A modified MOS REL structure, which explores the wired-OR property and enhances speed and power characteristics, is proposed. Proposed MOS REL gates have been fabricated and tested. It is shown that the power×delay of the MOS REL inverter is enhanced by 26%, with less silicon area
Keywords :
CMOS logic circuits; delays; logic design; logic gates; MOS REL gates; delay; modified MOS REL structure; power characteristics; recovered energy logic; speed characteristics; wired-OR property;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
DOI :
10.1049/ip-cds:19971288
