Performance issues in VC-merge capable switches for multiprotocol label switching

In a multiprotocol label switching (MPLS) domain, ATM label-switching routers (LSRs) are potentially capable of providing the highest forwarding capacity in the backbone network. Virtual circuit (VC) merging is a mechanism in an ATM-LSR that allows many IP routes to be mapped to the same VC label and provides a scalable mapping method that can support thousands of destinations. VC merging requires reassembly buffers so that cells belonging to different packets intended for the same destination do not interleave with each other. In this paper, the impact of VC merging on the buffering requirement for the reassembly buffers is investigated. We propose a realistic architecture that supports VC merging. We study the performance of this architecture using an analytic approach and using simulation driven by empirical Internet packet-size distribution. At the cell level, our main finding indicates that VC merging incurs a minimal overhead compared to non-VC merging, in terms of additional buffering. Moreover, the overhead decreases as utilization increases or as the traffic becomes more bursty with longer dependence. The finding has important practical consequences since routers and switches are dimensioned for high utilization and stressful traffic conditions. At the packet level, VC merging generally achieves a higher goodput than non-VC merging with EPD for the same buffer size. We also study the delay performance and find that the additional delay due to VC merging is insignificant at high speed