Multimode Reconfigurable Digital $\Sigma \Delta$ Modulator Architecture for Fractional- $N$ PLL

This brief presents the analysis, design, and implementation of a multimode reconfigurable digital Sigma-Delta (ΣΔ) modulator for use in fractional-N phase-locked loops. Analysis of second-, third-, and fourth-order modulators with respect to PLL phase noise contribution in the presence of loop nonlinearities is performed. Optimal architectures in each order are found and a single reconfigurable modulator is designed and implemented on FPGA. The proposed architecture is able to cover seven different modes of operation and spans three orders, thus offering a great degree of noise-shaping flexibility suitable for multistandard wireless applications. A case study for LTE/WiMAX is further presented for demonstration.