Title :
External Stresses on Tensile and Compressive Contact Etching Stop Layer SOI MOSFETs
Author :
Chang, Wen-Teng ; Wang, Chih-Chung ; Lin, Jian-An ; Yeh, Wen-Kuan
Author_Institution :
Dept. of Electr. Eng., Nat. Univ. of Kaohsiung, Kaohsiung, Taiwan
Abstract :
A n-/p-SOI MOSFET capped with a standard 380 Å tensile contact etching stop layer (CESL) and a 700 Å compressive CESL and with SOI thicknesses of 500/700/900 Å were measured in this paper. Additionally, external uniaxial compressive stresses with both longitudinal and transverse directions up to 45.7 MPa were applied on the devices sitting on cut silicon bars. Temperature-induced threshold voltage shifts and input-referred voltage noise showed bigger depletion zones and higher noise in the device with compressive CESL. The measurement suggests that both SOI thickness and CESL type are critical for mobility enhancement or degradation of devices. The capped compressive CESL for n-/p-SOI MOSFETs demonstrated higher piezoresistive coefficient compared with tensile CESL under external uniaxial compressive stresses for both longitudinal and transverse configurations.
Keywords :
MOSFET; etching; silicon-on-insulator; stress analysis; SOI thickness; compressive contact etching stop layer; external uniaxial compressive stress; input-referred voltage noise; mobility enhancement; n-p SOI MOSFET; piezoresistive coefficient; temperature-induced threshold voltage shifts; tensile stress; Bars; Compressive stress; Degradation; Etching; MOSFETs; Measurement standards; Silicon; Tensile stress; Thickness measurement; Threshold voltage; Contact etch stop layer; induced defect; piezoresistive; silicon-on-insulator (SOI) technology; strain engineering;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2010.2051362