DocumentCode
1526786
Title
Low power, high speed, charge recycling CMOS threshold logic gate
Author
Celinski, P. ; Lopez, J.F. ; Al-Sarawi, Said ; Abbott, Derek
Author_Institution
Dept. of Electr. & Electron. Eng., Adelaide Univ., SA
Volume
37
Issue
17
fYear
2001
fDate
8/16/2001 12:00:00 AM
Firstpage
1067
Lastpage
1069
Abstract
A new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design
Keywords
CMOS logic circuits; high-speed integrated circuits; logic gates; low-power electronics; threshold logic; 400 MHz; CMOS threshold logic gate; capacitive input latch; charge recycling logic gate; differential sense amplifier latch; high speed logic gate; low power logic gate;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20010742
Filename
948328
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