Title :
Low power, high speed, charge recycling CMOS threshold logic gate
Author :
Celinski, P. ; Lopez, J.F. ; Al-Sarawi, Said ; Abbott, Derek
Author_Institution :
Dept. of Electr. & Electron. Eng., Adelaide Univ., SA
fDate :
8/16/2001 12:00:00 AM
Abstract :
A new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design
Keywords :
CMOS logic circuits; high-speed integrated circuits; logic gates; low-power electronics; threshold logic; 400 MHz; CMOS threshold logic gate; capacitive input latch; charge recycling logic gate; differential sense amplifier latch; high speed logic gate; low power logic gate;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010742
