DocumentCode :
1527120
Title :
Novel radix-2k square root module
Author :
Bashagha, A.E.
Author_Institution :
Dept. of Eng. & Technol., De Monfort Univ., Leicester, UK
Volume :
148
Issue :
4
fYear :
2001
fDate :
8/1/2001 12:00:00 AM
Firstpage :
190
Lastpage :
196
Abstract :
The conventional two´s complement radix-2k square root algorithm requires a set of 2k full precision comparisons to generate all the 2k possible values of the partial remainder. The correct remainder is the minimum positive one of the 2k possible values. Since the number of adders of the 2k full wordlength comparisons increases exponentially with k, a huge area is required to implement this algorithm, especially for high values of k. The paper presents a new two´s complement high radix square root algorithm. For the first time, the 2k full wordlength additions are replaced with 2k one-digit (i.e. k-bit) additions only. It has been shown that the one-digit additions are enough to reduce the number of possible values of the partial remainder from 2k to two values only. Then, only two full wordlength additions are required to select the minimum positive value of these two values as the correct remainder. As a result, the silicon area is reduced significantly while the speed is nearly the same. Moreover, the new algorithm can be made faster by using one of the known fast adders because it requires only two (rather than 2k) full wordlength additions. From the evaluation of the proposed structure, it has been shown that the required area is reduced by 65% for radices of 32 and 64
Keywords :
digital arithmetic; adder; full wordlength addition; one-digit addition; silicon area; two´s complement radix-2k square root module algorithm;
fLanguage :
English
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2409
Type :
jour
DOI :
10.1049/ip-cds:20010453
Filename :
948390
Link To Document :
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