A low-power and high-speed dynamic PLA circuit configuration for single-clock CMOS

Author

Wang, Chua-Chin ; Wu, Chi-Feng ; Hwang, Rain-Ted ; Kao, Chia-Hsiung

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

Volume

46

Issue

7

fYear

1999

fDate

7/1/1999 12:00:00 AM

Firstpage

857

Lastpage

861

Abstract

Certain logic functions such as the control units of VLSI processors are difficult to implement by random logic. Since the programmable logic arrays (PLAs) can implement almost any Boolean function, they have become popular devices in the realization of both combinational and sequential circuits. We present a low-power high-speed complementary-metal-oxide semiconductor (CMOS) circuit implementation of NOR-NOR PLA using a single-phased clock. Buffering static NAND gates are inserted between the NOR planes to erase the racing problem and shorten the duration of glitches such that the dynamic power is reduced in addition to the low static power dissipation, no ground switch, no charge sharing, and zero offset

Keywords

CMOS logic circuits; high-speed integrated circuits; low-power electronics; programmable logic arrays; Boolean function; NOR-NOR PLA; buffering static NAND gates; dynamic power reduction; high-speed dynamic PLA circuit; low static power dissipation; low-power PLA circuit; programmable logic arrays; racing problem prevention; single-clock CMOS; zero offset; Boolean functions; CMOS logic circuits; Clocks; Combinational circuits; Logic devices; Logic functions; Power dissipation; Programmable logic arrays; Sequential circuits; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.774233

Filename

774233