• DocumentCode
    1528108
  • Title

    Corrections to “Unified Logical Effort—A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect” [May 10 689-696]

  • Author

    Morgenshtein, Arkadiy ; Friedman, Eby G. ; Ginosar, Ran ; Kolodny, Avinoam

  • Volume
    18
  • Issue
    8
  • fYear
    2010
  • Firstpage
    1262
  • Lastpage
    1262
  • Abstract
    In the above titled paper (ibid., vol. 18, no. 5, pp. 689-696, May 10), the formula and the caption in Fig. 3 appeared incorrectly. The correct figure is presented here along with an explanation.
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2010.2052421
  • Filename
    5499447
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1528108