Title :
Dynamic functional testing for VLSI circuits
Author :
Maurer, Peter M.
Author_Institution :
Univ. of South Florida, Tampa, FL, USA
Abstract :
The author discusses the two main problems of dynamic testing (i.e. testing while the simulator is running), namely the design of a high-level vector-generation language and the design of the interface between the vector generator and the simulator. He offers guidelines for designing a high-level vector-generation language as well as several examples written in FHDL, a driver language developed at the University of South Florida. The author also describes a solution to interface design that is based on a special interface data structure that supports several styles of vector generators and interactive circuit debugging.<>
Keywords :
VLSI; circuit CAD; integrated circuit testing; FHDL; VLSI circuits; dynamic functional testing; high-level vector-generation language; interactive circuit debugging; interface design; simulator; Circuit faults; Circuit simulation; Circuit testing; Debugging; Driver circuits; Guidelines; Logic testing; Signal generators; Switches; Very large scale integration;
Journal_Title :
Design & Test of Computers, IEEE
