Title :
Dynamic linear equaliser circuit
Author :
Sumesaglam, Taner
Author_Institution :
MS:FM7-222, Intel Corp., Folsom, CA, USA
Abstract :
A novel dynamic linear equaliser circuit is proposed for high-speed transceiver applications. The evaluation phase of a strong-arm latch is exploited to provide equalisation while sampling the input data. The circuit does not require any special biasing and only consumes power during transitions, which makes it superior compared to traditional continuous-time linear equalisers followed by samplers in terms of power efficiency and process scalability.
Keywords :
amplifiers; equalisers; flip-flops; transceivers; common source amplifier; continuous-time linear equalisers; dynamic linear equaliser circuit; high-speed transceiver applications; power efficiency; strong-arm latch;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2011.0922
