Preparation of silicon-on-gallium arsenide wafers for monolithic optoelectronic integration

Author

London, Joanna M. ; Loomis, Andrew H. ; Ahadian, Joseph F. ; Fonstad, Clifton G., Jr.

Author_Institution

Microsystems Technol. Lab., MIT, Cambridge, MA, USA

Volume

11

Issue

8

fYear

1999

Firstpage

958

Lastpage

960

Abstract

A process is described which combines silicon-on-insulator (SOI) and wafer bonding techniques to create thin (/spl ap/100 nm) single-crystal silicon layers on oxide coated gallium arsenide wafers for use in optoelectronic integration. Using a GaAs substrate for the integration eliminates the thermal expansion coefficient mismatch problems which have blocked monolithic integration of thick, stress sensitive optoelectronic devices on silicon, without compromising the performance of CMOS circuitry which can be fabricated in very thin, compressively strained silicon layers using SOT techniques.

Keywords

CMOS integrated circuits; III-V semiconductors; elemental semiconductors; gallium arsenide; integrated optoelectronics; optical fabrication; silicon; silicon-on-insulator; wafer bonding; 100 nm; CMOS circuitry; GaAs; GaAs substrate; SOT techniques; Si-GaAs; monolithic optoelectronic integration; optoelectronic integration; oxide coated gallium arsenide wafers; silicon-on-gallium arsenide wafers; silicon-on-insulator; stress sensitive optoelectronic devices; thermal expansion coefficient mismatch problems; thin single-crystal silicon layers; very thin compressively strained silicon layer fabrication; wafer bonding techniques; Application specific integrated circuits; CMOS integrated circuits; Diode lasers; Gallium arsenide; Monolithic integrated circuits; Optoelectronic devices; Silicon; Thermal expansion; Thermal stresses; Wafer bonding;

fLanguage

English

Journal_Title

Photonics Technology Letters, IEEE

Publisher

ieee

ISSN

1041-1135

Type

jour

DOI

10.1109/68.775312

Filename

775312